IBIS Macromodel Task Group Meeting date: 14 September 2021 Members (asterisk for those attending): Achronix Semiconductor: Hansel Dsilva Amazon: John Yan ANSYS: * Curtis Clark * Wei-hsing Huang Cadence Design Systems: Ambrish Varma Ken Willis * Jared James Google: * Zhiping Yang Intel: Michael Mirmak Kinger Cai Alaeddin Aydiner Keysight Technologies: Fangyi Rao * Radek Biernacki Ming Yan Todd Bermensolo * Rui Yang Luminous Computing David Banas Marvell Steve Parker Mathworks (SiSoft): * Walter Katz Mike LaBonte Micron Technology: * Randy Wolff * Justin Butterfield Missouri S&T * Chulsoon Hwang Siemens EDA (Mentor): * Arpad Muranyi Teraspeed Labs: * Bob Ross Zuken USA: Lance Wang The meeting was led by Arpad Muranyi. Curtis Clark took the minutes. -------------------------------------------------------------------------------- Opens: - None. ------------- Review of ARs: - None. -------------------------- Call for patent disclosure: - None. ------------------------- Review of Meeting Minutes: Arpad asked for any comments or corrections to the minutes of the August 31st meeting. Randy moved to approve the minutes. Bob seconded the motion. There were no objections. ------------- New Discussion: PSIJ modeling update: Chulsoon shared a presentation detailing new updates in their investigation into modeling PSIJ with IBIS. The presentation noted the original proposal presented last year, which introduced two new additive terms to the K(t) scaler functions. The two terms were linear and second order functions of the time averaged power rail voltage Vcc(t). Chulsoon noted two comments received as feedback when the proposal was first presented to ATM. First, the Ku and Kd coefficients presented had not settled to 0 and 1 as their initial and steady state values. This had been rectified in the new investigation by using a different tool for the simulations from which which the curves were extracted. The second comment(s) centered around the use of the typ, min, max corners for I-V and V-T data. Commenters noted that corners were for process, voltage and temperature variations, and their use in the computation of the new linear and second order terms for the PSIJ correction could be problematic (Note: the systems of equations set up to compute the new linear and second order coefficients had relied on mixing curves from different pvt corners): - The t=0 reference might not be the same across typ/min/max - typ, min, max variations represent process and temperature, not just voltage. To address these concerns a new approach was introduced. Instead of the two new terms in the K(t) equations, the proposal introduces a new [PSIJ] keyword that contains the sensitivity of the timing of the edge to changes in Vcc (units s/V). To compute the K(t) coefficients incorporating the PSIJ, the existing K(t) coefficient functions are used, but the time argument is shifted by an amount based on the difference between the time averaged value of Vcc(t) since the last transition and the nominal Vcc. Ku(t) = Ku0(t + deltaVcc * PSIJ) Chulsoon noted that the [PSIJ] keyword provides the jitter sensitivity at DC for the entire buffer path. The keyword could also provide typ, min, max corner values. Walter said he welcomed the introduction of the [PSIJ] keyword and a linearized jitter sensitivity value. However, he asked if the implementation described was necessary. He said in a typical system simulation the spectral density of the rail voltage might be provided. The engineer making decisions might simply apply that as a gaussian jitter based on a scale factor. He said the proposed approach would likely give a more precise waveform that you can correlate with lab measurements, but would it allow the system engineer to make a better design decision? Walter said there would be effort involved for EDA tools to support the new [PSIJ] keyword in a time domain simulation, so we should know what the benefits are relative to a traditional margin analysis. Arpad said he too welcomed anything that would improve accuracy. However, he noted that high speed modeling was often being done with AMI. With AMI the legacy IBIS [Model] and keywords are used for determining the step response, and this would not take PSIJ into account since a single step response is computed. He asked whether most people were using AMI and would incorporate PSIJ effects using AMI Reserved Parameters for jitter, along the lines of Walter's comments about budget analysis (post processing vs. time domain waveform simulation). Chulsoon said he thought that as designs advanced the margins were dropping and it was increasingly hard to analyze the systems with basic budget analysis. Randy said that many people use AMI, but there are still many people who do full time-domain waveform simulations with traditional IBIS. He said with power aware IBIS modeling you can get pretty good correlation with SPICE. He said this PSIJ issue is probably the largest remaining issue for improving agreement with SPICE. Radek said that he didn't think the new proposal for PSIJ modeling would be very hard for tools to implement. Walter said if the goal is to improve correlation with SPICE, this proposal will do that. The question is whether it will help IBIS provide engineers with better answers. Walter said he was all for the [PSIJ] keyword information, but he said the tool might be able to use it in different ways. For example, an EDA tool might also be able to shift the edges of the stimulus waveform input to Tx GetWave. If the tool also had access to the voltage rail waveform it could compute the shifts in the stimulus waveform edges accordingly. Zhiping said this proposed technique is modeling the SI and PI interaction. He said the more functionality we can get from the IBIS Model the better, as vendors often only supply IBIS models not SPICE models. Randy asked if the intent was that the value of [PSIJ] could be positive or negative to indicate which way the edge shifts in response to a voltage change. Chulsoon said that was the intent. Bob noted that the example plots showing correlation with SPICE only showed a rising edge transition. Radek said it would be good to have more test cases showing SPICE correlation. Arpad asked if different buffer architectures had been tested (current driver, totem pole, CMOS pushup and pulldown, etc.). He also asked about differential and single-ended cases, and he said he thought differential drivers tended to be less sensitive to PSIJ. Chulsoon said investigations so far had focused on CMOS. He said that there will be cases when this approach might not work. He noted that term 2 on slide #7, the frequency dependency based on the power supply rejection ratio, is assumed to be negligible. He said this assumption might not work for some architectures. Chulsoon said they would be performing validation testing on more device models. Walter said we typically think of a buffer as a whole bunch of stuff in front of the final CMOS transistor. He asked if this induced delay is in the final CMOS transistor or the rest of the path in the buffer. Arpad said this was likely a pre-driver effect. Randy said there are buffers where what's driving the gate of the final driver is on a different power rail than that used by the final driver. In those devices, this PSIJ effect is zero. However, in other devices you have multiple gates using the same voltage as the I/O. In those cases you would see this kind of jitter. Arpad said modulating the pre- driver's supply rail could cause the effect in the types of devices Randy had first described. Randy agreed but said in those cases the pre-driver supply rail is not being affected by the I/O supply. Walter said the buffer models don't normally have that pre-driver circuitry. They normally just have the final CMOS transistor. Arpad asked if it would help if any vendors could provide transistor level models for correlation. Chulsoon said any collaboration of that type would be welcome. Randy said he thought he had some study data on these effects that he might be able to check against Chulsoon's results. - Randy: Motion to adjourn. - Walter: Second. - Arpad: Thank you all for joining. AR: Chulsoon to email his presentation to ATM. ------------- Next meeting: 21 September 2021 12:00pm PT ------------- IBIS Interconnect SPICE Wish List: 1) Simulator directives